The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC SOC Designs and is considered as a key skill for any job in the front end VLSI design verification jobs.
What are the course deliverables ?
Over 36 lectures and 5.5 hours of content
Understanding of the concepts behind OVM and UVM Verification methodologies
Coding and building test benches using UVM or OVM Verification methodology
Who should do this course ?
Verification engineers who have basic understanding of System Verilog but are new to OVM/UVM methodology
Students passing out of VLSI/Digital Design/Microelectronics looking for a front end job in VLSI design
Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills
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